IP core design of 8253 based on quartus II

doi:10.4028/www.scientific.net/AMM.380-384.2941

CQUET-IR

	IP core design of 8253 based on quartus II
	Zhang, Hai Yan
	2013
会议录名称	Applied Mechanics and Materials
卷号	380-384
页码	2941-2944
会议名称	2013 International Conference on Vehicle and Mechanical Engineering and Information Technology, VMEIT 2013
会议日期	August 17, 2013 - August 18, 2013
会议地点	Zhengzhou, Henan, China
出版者	Trans Tech Publications Ltd, Kreuzstrasse 10, Zurich-Durnten, CH-8635, Switzerland
摘要	Provided by ALTERA FPGA/CPLD Quartus II development software development platform, programmable timer/counter 8253's functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design, The completed design will be configured to the chip of FLEX10KE,and Proved to be correct. © (2013) Trans Tech Publications, Switzerland.
关键词	Computer hardware description languages Field programmable gate arrays (FPGA) Information technology Schematic diagrams 8253 FLEX10KE Internal circuitry Parameterized Programmable gate array Programmable timer Quartus II VHDL
DOI	10.4028/www.scientific.net/AMM.380-384.2941
收录类别	EI
语种	英语
EI入藏号	20134116829217
原始文献类型	Conference article (CA)
文献类型	会议论文
条目标识符	https://ir.cqcet.edu.cn/handle/39TD4454/3332
专题	重庆电子科技职业大学
作者单位	Communication Engineering Department, Chongqing College of Electronic Engineering, Chongqing, 401331, China
第一作者单位	重庆电子科技职业大学
推荐引用方式 GB/T 7714	Zhang, Hai Yan. IP core design of 8253 based on quartus II[C]:Trans Tech Publications Ltd, Kreuzstrasse 10, Zurich-Durnten, CH-8635, Switzerland,2013:2941-2944.